module RAM (
	input [9:0] address,
	input [31:0] data_in,
	input write_enable,
	input clk,

	output [31:0] data_out
);
	reg [31:0] memory[1023:0];

	assign data_out = memory[address];

	always @ (posedge clk) begin
        if (write_enable) begin
            memory[address] <= data_in;
        end
    end
endmodule